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Race Result Details |
| Racer | Athens (creamymochi) |
| Race Number | 9 |
| Date | Mon, 2 Oct 2017 21:09:03 +0000 |
| Speed |
58 WPM
 Try to beat?
|
| Accuracy | 97.3% |
| Rank | 5th place (out of 5) |
| Opponents | darkknight64 (2nd place) gmdliam (3rd place) vetlebg (1st place) |
Text typed:
 
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In synchronous communications, the sender and receiver must synchronize with one another before data is sent. To maintain clock synchronization over long periods, a special bit-transition pattern is embedded in the digital signal that assists in maintaining the timing between sender and receiver.
— Encyclopedia of Networking and Telecommunications
 (book)
by Tom Sheldon
(see stats)
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